The present disclosure relates to a test system and, more particularly, technology for providing a repair address to a semiconductor memory device in a test operation mode.
In fabricating a semiconductor integrated circuit, various procedures including design, process, package, and test are necessary. Moreover, the test is categorized into a functional method, a parameter method, and a burn-in method. In these methods, semiconductor integrated circuits may be tested in a wafer, in die, or in a package form. Although the package is a relatively cheap procedure, semiconductor makes typically package devices before testing, that is, before determining proper operations of the semiconductor integrated circuit devices. Considering the complexity of the structures of semiconductor integrated circuit devices, however, and due to the high cost necessary for packaging semiconductor integrated circuit devices, the devices need to be tested with a wafer or die form to reduce the probability of packaging abnormal semiconductor integrated circuit devices. Further, in connection with the advent of multichip modules, a wafer or package test certainly is required since a semiconductor integrated circuit device is only one of the elements mounted on a multichip carrier.
FIG. 1 is a flowchart useful for describing a conventional test method.
Referring to FIG. 1, a test device may write test pattern data in a semiconductor integrated circuit device for example a semiconductor memory device, to be tested according to a given timing (S10). Then, the test device reads test pattern data written in the semiconductor memory device (S20). The test device judges whether the read test pattern data includes fail data (S30). The presence of fail data may be judged by comparing the read test pattern data with the written test pattern data. Defective cells of the semiconductor memory device corresponding to the fail data may be repaired with redundant cells (S40).
In order to repair defective cells of a semiconductor memory device, a conventional test device may provide addresses of the defective data to a semiconductor memory device under test via an address bus. Hereinafter, an address for defective data is referred to as a defective address or a repair address. Defective addresses from a test device may be stored in a redundancy circuit of a semiconductor memory device. The redundancy circuit includes electric fuses that are selectively cut according to the input defective addresses, which are stored in the redundancy circuit by selective cutting of electric fuses.
In general, vector address information is stored in a test device to appoint each cell of a semiconductor memory device under test. The vector address information includes addresses for appointing all cells in the semiconductor memory device under test. At a repair step, the test device may provide the semiconductor memory device under test with address information that coincides with a defective address of the vector address information. Generally, the stored space of the test device for storing vector address information is limited. As the storage capacity of a semiconductor memory device is gradually increased, its vector address information is also increased. Accordingly, it is hard to test a semiconductor memory device with increased storage capacity using a test device with a limited storage space. Further, in a case where a test device does not have a function for comparing vector address information with an address of defective data, it is impossible to repair defective cells of a semiconductor memory device.